The system has a frequency-sliced structure very similar to the current Plateau de Bure equipment. It is made of a number of identical units, each of them being able to completely process a slice of frequency ranging from 320 to 40 MHz. The chosen number of units is 8, which allows full band dual-receiver observation and matches well the VLBI recording requirements.
The selected IF signal from each antenna is delivered to each unit's input via a 48-arm central coaxial distribution system. Each unit can activate the proper switches in the distribution boxes so as to work on either IF. The 8 units are laid out on a circular table so as to preserve timing equity.
One unit is made out of an IF processor which selects and digitizes the frequency window of interest, and a digital chassis. From the previous (1992) design, there are two significative differences: a) the samplers have been attached to the IF processor in order to improve the cleanliness of the sampling, and b) the phase rotators are of DDS+PLL type in order to get a more accurate real-time phase tracking.
The use of new, more integrated technology at both analog and digital level will allow significant benefits from a user's point of vue whilst keeping the project a reasonable size.
Improvement highlights: (versus 1996 status)
- Global bandwidth: 2.56GHz (0.96 GHz)
- Flexibility : 8 units (6), channel spacings in powers of 2 sequence (of 4)
- Global digital performance: 9.8 Teramultiplications per second (1.3)
- 6 antennas, tied array mode capability.
The 48-arm central distribution system
The signal input is in the range 100-1100MHz. The 320 MHz band of interest is upconverted in the 1120-1440 MHz range by a 1540-2360 MHz LO3 synthesizer with a step size of 0.25 MHz. The band is selected by a bandpass filter and sent with the LO4 to an IRM (also called SSB mixer or also BBC for baseband converter) which converts it into two basebands 0.005 to 160 MHz. The very low cutoff frequency (5 kHz) is for the VLBI phasecal signal at 10 kHz to be transmitted. This implies some additional difficulty in the already complex 90 degree LC phase shifting network. The output ports are labeled U and L, with the convention that a signal applied at the input of the IRM would appear at the U port when its frequency is less than the value of the LO4. The LO4 operates at the fixed frequency of 1280.260MHz, plus the residual fringe frequency which comes from the DDS board of the digital chassis.
The six upconverters and the six PLL's are located in the same type of specially machined housing, which has a lower deck consisting of six isolated enclosures, communicating with the single upper deck via drillings. This kind of "dual-faced" microwave assembly offers good crosstalk protection, and saves a lot of space and connectors. The LO3 and LO4 synthesizers and their 6-way distribution circuits are located in the upper decks.
The samplers and their set of 4 programmable lowpass antialiasing
are built in a single module, located in the IF processor rack in order
to isolate the fragile analog signals from the highly-radiating
which takes place in the digital chassis. The clipping voltages are
at 0.5 Volts but the amplitude of the signal is varied under the
of a 12-bit D-to-A, which drives an electronic attenuator. The last
stages are DC-coupled to prevent asymmetrical clamping. The sampler
are duals (U+L), in order to share some circuitry. The 4 digitized
at 320 Ms/s are sent via 8-line differential RJ-45 connectors .
The whole IF processor rack is controlled by the unit CPU ,via a I2C serial bus.
. Dual delay line boards
. Correlator board
. Clock and phase rotator board
. Adder and control board
Dual delay line boards
They accept the digitized data at 320 Ms/s from the samplers, located in the IF processor. One board takes care of two sidebands (U and L) and two antennas. The 320 MHz clock is distributed by the neighbour board to the ECL front end of each sideband which consists of a 4-cell serial to parallel converter, clocked by the backplane general 80 MHz clock . The data is stored in a delay line FPGA chip which provides 4096 steps 3.125 nsec each. This corresponds to a light travel of 3840 m. Inside the FPGA the data is actually written in an 8Kbyte RAM clocked at 20 MHz and serialized to 80 MHz after. The FPGA includes the pointers, and the delay register double buffers. The data (32-bit) is delivered at 80 Msamples/sec to the backplane by 4 octal power line drivers .
The interferometer needs 15 baselines to be processed. The chosen system structure is such that each baseline is processed by a dedicated board. Each correlator board needs to receive two operands (16 bits each) from a set of six. This represents a total of 480 connexions. They are implemented in stripline technology on a multilayer specific backplane. The length of the backplane imposes a traveling time of 2.4ns, compared to a bit time of 12.5ns. This can be divided by two if the signals travel from the middle of the chassis to the edges. Regarding eye diagrams, the whole chassis can then be considered iso-temporal. Nevertheless it is wise that both clock and timing signals travel from middle to edges so as some cancellation of delay can occur. The system clock which needs more care is distributed in differential ECL, with one buffer per half chassis. Two correlator boards never need concatenation, and this simplifies the timing problems a great deal. The principal speed limitation of this interconnection technology comes from the edge connectors.
The correlator board hosts 16 chips with the associated I/O and data
bus circuitry. Interconnections can support time-multiplex factors of
and 8. The operating clock speed is 80 MHz but it can be safely
at 125 MHz at the expense of a slightly higher chip temperature. The
power dissipation at 80 MHz is a very low 6.4 Watts. Chip dissipation
The board can perform several modes as shown by the following table :
|Bandwidth||Sub-band||Correlator clock||Time Multiplex Factor||Lags number||Complex channels||Channel spacing|
|2 x 160 MHz||LSB + USB||80 MHz||4||2 x 128||2 x 64||2.5 MHz|
|1 x 160 MHz||LSB or USB||80 MHz||4||1 x 256||1 x 128||1.25 MHz|
|2 x 80 MHz||LSB + USB||80 MHz||2||2 x 256||2 x 128||0.625 MHz|
|1 x 80 MHz||LSB or USB||80 MHz||2||1 x 512||1 x 256||0.312 MHz|
|2 x 40 MHz||LSB + USB||80 MHz||1||2 x 512||2 x 256||0.156 MHz|
|1 x 40 MHz||LSB or USB||80 MHz||1||1 x 1024||1 x 512||0.078 MHz|
|1 x 20 MHz||LSB or USB||40 MHz||1||1 x 1024||1 x 512||0.039 MHz|
Clock and phase rotator board
This board generates the timing signals for the digital section and
the phase-controlled references for the LO4 PLL's. Both are derived
the 320MHz clock and 1pps inputs, under the control of the VME bus. The
320 MHz clock from the IF processor chassis is copied 3 times to feed
3 delay line boards. The 80 MHz, which clocks the whole correlator, is
not generated locally, but sent by the IF processor so as to ensure the
same phase on all units. It can be set to 40 MHz when the 20 MHz BW
is selected. The residual fringe rates applied on the LO4's are
at the intermediate frequency of 260 kHz by means of DDS chips. These
essentially binary accumulators so to deliver exactly integer Hz
(traditional in VLBI applications) they need a clock value which is a
of two. This clock value is chosen to 2^22Hz so as one LSB of the rate
control word gives a maximal accumulated phase error of 0,3 degrees
being re-written (every second) . This clock (4.19... MHz) is derived
a phase-locked VCXO. The 6 DDS are followed by DACs and on-board
(40 kHz) filters so as to deliver a sinewave to the PLLs located in the
IF processor rack.
This boards also hosts the VME control circuitry, interrupt generator and VME to I2C interface.
The adder board takes the sampled data of the 6 antennas from the
and performs the sum in a FPGA. It later converts it to analog via a
D-to-A, to be sent to the VLBI formatter.
The analog section of the adding network is carefully shielded to prevent contamination from the digital activity. A 10 kHz monitor output is provided on the front panel, which is very useful for checking the phase stability of the LOs involved in VLBI, and the proper frequency setting.
Phased array mode specific
. General setup
. 1 MHz phase calibration signal
. Residual fringe compensation
. Assignation of one antenna as a reference
. Walsh function Pi phase switching
. Addition process
The basic idea is to replace the IF processing equipment (synthesizers, BBC's) which is part of a VLBI recording terminal by the same elements which are already available from the local correlator. The addition is performed on the digital samples representing data with delays and phases already corrected for, as it is usual for local correlator work.
For a VLBI experiment, each correlator unit is assigned to a specific frequency band and is used as a summing device equivalent to one baseband converter (BBC) of the classic, single-dish terminal. The recorder is directly fed by analog signals (0 to 16 MHz) entering its own digitizer.
The major difference with connected interferometry is that the
phase of the digitized data not only needs to be constant (versus time
and frequency) but constantly equal to zero, so that the addition can
performed properly. During every pause of the recording session the
correlator is used to check the quality of this zero.
The design of the LO synthesizers is such that the LO phases are defined absolutely with respect to the master (and Maser) frequency standard.
1 MHz phase calibration signal
It is a tradition that the VLBI frequency setups are such that the
of the basebands to be recorded correspond to sky frequencies of
MHz minus 10 kHz (e.g. 86534,990 MHz). It is assumed that the
and IF equipment offsets the sky frequency into IF3 by some value
to as net LO) which is an integer number of MHz. Then the 1 MHz
"pcal" signal injected at IF3 exits the BBC at a frequency of (LO3 -
-LO4), which is 10 kHz on the USB port. Since LO4 is fixed to 1280.260
MHz, this is true only for those LO3 frequency values of the form
MHz. The 8 units may be set at a 32 MHz spacing to cover the maximal
MHz band. Since the step of the LO3 is 0.25 MHz, any integer MHz
(e.g.: 4,8,16) is possible.
Residual fringe compensation
The insertion of a digital delay at the baseband level causes a
fringe which is usually (in connected interferometry) compensated for
rotating the phase of the relevant LO3. This would create a phase drift
of the received signals, and of the 10 kHz tone as well, different for
each subband. Of course the other observatories involved in a VLBI
do not add this rotation, so the recorded phase would not be consistent
with them. Furthermore, since the 1 MHz comb is injected globally on
IF3, the phase relationship of the 10 kHz signals in the different
would vary with time, thus puzzling the off-line correlator.
Assignation of one antenna as a reference
A way to solve this problem is to assign the phase center of the array at one particular antenna instead of having it at the center of gravity of the array as it is done usually. This antenna has its main and residual phase rotators steadily set to zero, its delay set to midrange, and the 1 MHz rail is injected in its IF through a coupler. Then this antenna appears to the VLBI correlator like a common single-dish.
Prior to recording, the instrumental phases are measured on a celestial source by the local correlator and set to zero. During the recording, the software sets the proper delays, rates and phases to all other antennas with respect to the reference antenna so that the addition process can perform constructively. The phases and amplitudes of the sky signal delivered by the local correlator are displayed on-line, so the operator can visually monitor that the phasing process is working properly. This display also provides interesting information on the atmospheric stability during the recording.
The basic difference between this technique and the usual one lies in the incremental nature of the fringe tracking over an extended period of time. In the connected interferometer we have a hard reset of the phases followed by an incremental run every second. During the VLBI recording session, no hard reset is allowed, so the system (hardware + real-time software) must deliver a phase-continuous LO signal which stops the fringes over the whole recording duration (1000 seconds between pauses are typical).
Having independent units used as BBCs offers the possibility
assigning one pair of tracks to the reference antenna only. Should the
phased array process misfunction, this pair of tracks would give useful
debugging information. Incidentally this could provide a
of the global efficiency of the summation process, by comparing the
ratios from the "single-element" and "tied array" tracks of the tape.
Walsh function Pi phase switching
In connected interferometry this chopping is essential to remove
crosstalks that would appear as offsets of the tiny sky signal. The
process is one order less affected by crosstalks and does not call for
Pi switching. Nevertheless, it is very useful to simultaneously operate
the local correlator during the recording session, although in
only the summed output is needed. Operation of the local correlator
Pi switching. The phase switching is encoded at the 1st LO and decoded
in the digital section. Since the 1MHz phasecal signal is applied in
it would be chopped and thus not usable.
This problem is solved by taking advantadge of the fact that any arbitrary phase can be added simultaneously to all the arms of the local interferometer. So it has been chosen to operate the Walsh switching sequence as usual, plus to add on all antennas the necessary phase to let the reference antenna appear unmodulated.
Since the 1 MHz rail signal is applied only on one antenna, some dilution of its power takes place while being added to the other antennas. This is corrected for by injecting more power (an estimated 16 dB).
The addition process takes place in a digital look-up table which has been optimized for minimal degradation of the output 6-bit signal. All antenna temperatures are assumed to be the same. Signals from antennas that might not be serviceable on the day the session starts can be zeroed to prevent corruption of the sum. Then the amplitude loss is compensated for in a digital multiplier.
The data has been considerably oversampled (20 MHz,320 Ms/s). This allows for a 3 nsec delay resolution which causes a 9 degree maximal error at 16 MHz. The data at 320 Ms/s is actually represented on the backplane by four samples at 80, and the adder only takes each fourth one. Each data line has a sign inverter to demodulate the Walsh PI switching.
The output wave is reconstructed at 80 Ms/s and lowpass filtered by built-in 16, 8 or 4MHz filters. For special experiments a special filter can be built out. This oversampling, together with the random composition of the 6 channels, contributes to deliver a quasi-analog output. The sampled D-to-A conversion creates a frequency response rolloff (sinx/x) of less than 1 dB. This is roughly equalized by an analog network.
Unfortunately this reconstructed analog signal is digitized again (in 1.6 bit mode) in the Mark IV formatter.